Intellectual Property Law

US Patent 7728626 - Nanolaminate transistor logic array

This patent from Micron teaches a transistor architecture using nanolaminate charge trapping structures for higher density programmable logic. Claim 1 reads:

1. A programmable logic array, comprising:

a plurality of input lines for receiving an input signal;

a plurality of output lines; and

one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal,

wherein each logic cell includes a transistor cell including:

a first source/drain region;

a second source/drain region;

a channel region between the first and the second source/drain regions, and

a gate separated from the channel region by a gate insulator; and

wherein the gate insulator includes oxide insulator nanolaminate layers wherein at least one charge trapping layer in the oxide insulator nanolaminate layers is substantially amorphous.

Full post as published by TinytechIP on June 09, 2010 (boomark / email).